1. Field of the Invention
The present invention relates to a technique for extending the life of electronic circuits. As an applied example thereof, the present invention relates to a scanning circuit of a display device and, more specifically, to a scanning circuit formed with a single conductive type thin film transistor.
2. Description of the Related Art
Display devices using amorphous silicon thin film transistors (referred to as “a-SiTFT (amorphous Silicon Thin Film Transistor)” hereinafter) are used broadly from small-sized panels of mobile apparatuses monitors and the like, to monitors for personal computers, large-sized panels of large-screen thin-type television sets and the like. In general, only the pixel array constituting the display area is formed with a-SiTFT, and an IC (Integrated Circuit) chip is used for the gate driving circuit for driving the pixels.
Recently, development of the techniques for forming the gate driving circuit simultaneously with the pixel array are being advanced in order to cut the manufacturing cost of the display and to decrease the frame length (distance from the external shape of the display to the display area). In the typical gate driving circuit formed with a-SiTFT, dynamic scanning circuits as disclosed in following Patent Documents are used.
The scanning circuit of U.S. Pat. No. 5,222,082 (FIG. 2, 37th row of second column to 27th row of third column: Patent Document 1) will be described by using FIG. 20 as Related Technique 1.
As shown in FIG. 20, the scanning circuit of Patent Document 1 is an example of the dynamic scanning circuit formed with single conductive type transistors 516 to 521, in which a plurality of stages 511 are connected in series.
When an input signal INPUT is turned to high level, the transistors 518 to 521 are both turned into an on-state. Thereby, a node P1 is set to VDD−Vth and a node P2 is set to VSS, respectively. Note that Vth is a threshold voltage of the transistor 518. Due to the potential increase of the node P1, the transistor 516 is turned into an on-state. Further, since the node P2 is turned to VSS, the transistor 517 and 519 come to be in an off-state.
Subsequently, when the input signal INPUT is turned to low level, the node P1 comes to be in a floating state. When a clock signal C1 is turned to high level from low level in that state, the potential of an output signal OUTPUT1 becomes increased. In that state, the potential of the node P1 in the floating state is also increased due to a bootstrap effect via the parasitic capacitance (not shown) between the node P1 of the transistor 516 and the node P3 (OUTPUT1). Thus, when the node P1 is increased to the potential higher than the high level, a high-voltage signal is applied to the gate of the transistor 516. Therefore, the high level of the clock signal C1 is transferred as the output signal OUTPUT1 without being attenuated.
Subsequently, when a clock signal C3 is turned to high level, the transistor 520 comes to be in an on state. Thus, the node P2 is set to VDD−Vth. Note here that Vth is the threshold voltage of the transistor 120. Thereby, the transistors 517 and 519 come to be in an on-state, so that the node P1 and P3 (OUTPUT1) are set to VSS, respectively. This makes it possible to prevent malfunctions of the circuit.
With the structure of Patent Document 1, the transistors 517, 519 are always in an on-state while the output signal OUTPUT1 is in low level and pull down the nodes P1, P3 (OUTPUT1) to VSS. That is, a high-level voltage is applied to the gates of the transistors 517, 519, while a low-level voltage is applied to the sources or the drains. This bias state is called hereinafter “plus gate stress”. For example, when the circuit is formed with a-SiTFT, there is such an issue that the fluctuation of the threshold voltage becomes great due to the “plus gate stress”.
Japanese Unexamined Patent Publication 2008-262178 (FIG. 3, paragraphs 0048 to 0058: Patent Document 2) and Japanese Unexamined Patent Publication 2010-534380 (FIG. 1, paragraphs 0034 to 0040: Patent Document 3) as Related Techniques 2, 3 disclose proposed solutions for such issue raised in Patent Document 1. The scanning circuit of Patent Document 2 will be described by referring to FIG. 21.
As shown in FIG. 21, Patent Document 2 employs a structure in which, out of two transistors 612, 613 of an output circuit 611 within a shift register 610, a voltage generating circuit 300 is connected to the gate of the transistor 612. The voltage generating circuit 600 is constituted with a judging circuit 601, an impedance converter 607, and a voltage setting circuit 620. Further, the voltage setting circuit 620 is constituted with a controller 602, an adder 603, a counter 604, and a DA converter circuit 606.
Further, the judging circuit 601 detects the operation state of the transistor 612, and the voltage setting circuit 620 controls the voltage to be supplied to the gate of the transistor 612 according to the detected result. That is, Patent Document 2 discloses that it is possible to increase the voltage to be applied to the gate of the transistor 612 according to the property fluctuation of the transistor 612 by providing the judging circuit 601 and the voltage setting circuit 620.
The scanning circuit of Patent Document 3 will be described by referring to FIG. 22.
As shown in FIG. 22, the scanning circuit of Patent Document 3 includes: a row pullup transistor 710; a bootstrap capacitor 711; a row pulldown transistor 712; a transistor 713 which charges the bootstrap capacitor 711; a transistor 714 which regenerates the state of the row pulldown transistor 712; a Vt detecting circuit 716; a positive voltage line 718; a negative voltage line 719; control lines 1 to N; and the like.
The Vt detecting circuit 716 detects the threshold voltage Vt of the row pulldown transistor 712, and supplies an output signal Vout that is acquired by adding or subtracting an offset value ΔV to/from an input signal Vin to the gate of the row pulldown transistor 712.
However, when the circuit structures disclosed in Patent Documents 2 and 3 are applied to a scanning circuit constituted with a single conductive type thin film transistor, a following issue is raised.
The scanning circuits of Patent Documents 2, 3 are designed to compensate the current driving capacity of the transistor by increasing the voltage to be applied to the gate according to the detected threshold voltage of the transistor.
According to the experiments done by the inventors, et al. of the present invention, it is verified that the fluctuation in the threshold voltage of the transistor becomes greater as the absolute value of the voltage to be applied to the gate becomes higher. This is considered because the electric stress imposed upon the transistor becomes also greater as the absolute value of the voltage to be applied to the gate becomes higher.
Because of that, with the structures of Patent Documents 2, 3, the electric stress imposed upon the transistor becomes larger than that of before the detection because the voltage to be applied to the gate is increased during the action of the circuit. Thus, more fluctuation in the threshold voltage is generated. Therefore, there is such an issue with the structures of Patent Documents 2 and 3 that the circuit life of the scanning circuit cannot be extended sufficiently.
It is therefore an exemplary object of the present invention to provide an electronic circuit and the like capable of extending the life greatly even when there is fluctuation in the property of the transistor that forms the electronic circuit.